A 1.2 Gb/s/pin double data rate SDRAM with on-die-termination-Reference-Cited by-同舟云学术

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A 1.2 Gb/s/pin double data rate SDRAM with on-die-termination

Published: Issue: Volume: Page:
ISSN:
Container-title:2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.
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Author:

Ho Young Song ,Seong Jin Jang ,Jin Seok Kwak ,Cheol Su Kim ,Chang Man Kang ,Dae Hyun Jeong ,Yun Sik Park ,Min Sang Park ,Kyoung Su Byun ,Woo Jin Lee ,Young Cheol Cho ,Won Hwa Shin ,Young Uk Jang ,Seok Won Hwang ,Young Hyun Jun ,Soo In Cho

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/8736/27661/01234314.pdf?arnumber=1234314

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1. Time Controlled Pre-Emphasis Circuit for Broadband Frequency Operation up to 3.6 Gbps;2023 20th International SoC Design Conference (ISOCC);2023-10-25

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