A 0.004mm2 250μW ΔΣ TDC with time-difference accumulator and a 0.012mm2 2.5mW bang-bang digital PLL using PRNG for low-power SoC applications
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/6171933/6176863/06176992.pdf?arnumber=6176992
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Design of a third-order delta-sigma TDC with error-feedback structure;IEICE Electronics Express;2019
2. High‐precision differential time integrator based on time adder;Electronics Letters;2018-11
3. A 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter Utilizing Two-Step Transition Inverter Delay Lines in 28 nm CMOS;IEICE Transactions on Electronics;2017
4. A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring;IEICE Transactions on Electronics;2017
5. CMOS time‐to‐digital converters for mixed‐mode signal processing;The Journal of Engineering;2014-04
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