Design and Implementation of High-Performance PnR Block-Level Design with Timing Placement
Author:
Affiliation:
1. Kalasalingam Academy of Research and Education,Department of ECE,Krishnankoil,Tamilnadu,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10142228/10142218/10142497.pdf?arnumber=10142497
Reference18 articles.
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4. Efficient IP Routing Table VLSI Design for Multigigabit Routers
5. Block Level Physical Design of Interfacing Module in RISC Core;aland,2012
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