10 GB MAC Core Verification Monitor Module
Author:
Affiliation:
1. Kalasalingam Academy of Research and Education, Krishnankoil,Department of Electronics and Communication Engineering,Virudhunagar,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10142228/10142218/10142532.pdf?arnumber=10142532
Reference18 articles.
1. CSPR Using in Delay Tolerant Networks;anushuya devi;International Journal of Electronics Communication and Computer Engineering (IJECCE),2013
2. Gigabit ethernet switches using a shared buffer architecture
3. Multi Modal Biometric Security for Mobile Ad-hoc Networks;deny;International Conference on Emerging Novelties and Vistas in Space Technologies and Applications “ENVIST A 2016”,0
4. UVM based STBUS verification IP for verifying SoC architectures
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1. UVM Based Verification of an Ethernet MAC using Wishbone Bus;2024 IEEE 13th International Conference on Communication Systems and Network Technologies (CSNT);2024-04-06
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