Engineering TID modeling for the SEE and performances evaluations of integrated CMOS circuits at cryogenic temperatures-Reference-Cited by-同舟云学术

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Engineering TID modeling for the SEE and performances evaluations of integrated CMOS circuits at cryogenic temperatures

Published:2019-09 Issue: Volume: Page:
ISSN:
Container-title:2019 19th European Conference on Radiation and Its Effects on Components and Systems (RADECS)
language:
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Author:

Artola L.¹,Ducret S.²,Hubert G.¹

Affiliation:

1. ONERA / DPHY, Université de Toulouse,Toulouse,France,F-31055

2. Lynred,Veurey-Voroize,France,38113

Funder

ONERA

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9745606/9745637/09745704.pdf?arnumber=9745704

Reference17 articles.

1. Single-Event Transient Modeling in a 65-nm Bulk CMOS Technology Based on Multi-Physical Approach and Electrical Simulations

2. Single Event Upset Sensitivity of D-Flip Flop of Infrared Image Sensors for Low Temperature Applications Down to 77 K

3. Two-dimensional methodology for modeling radiation-induced off-state leakage in CMOS technologies

4. Modeling Ionizing Radiation Effects in Solid State Materials and CMOS Devices

5. Characterization and Modeling of Gigarad-TID-Induced Drain Leakage Current of 28-nm Bulk MOSFETs

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