Silicon Isolation Trench Integration for the 4-stack Memory Wafer-Reference-Cited by-同舟云学术

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Silicon Isolation Trench Integration for the 4-stack Memory Wafer

Published:2021-12-07 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC)
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Author:

Wang Xiangyu,Kawano Masaya,Chandra Rao B.S.S.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9663571/9663865/09663912.pdf?arnumber=9663912

Reference3 articles.

1. Yield Improvement of Silicon Trench Isolation for One-Step TSV

2. Trench Isolation Technology for Cost-effective Wafer-level 3D Integration with One-step TSV

3. New Cost-Effective Via-Last Approach by "One-Step TSV" After Wafer Stacking for 3D Memory Applications

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Wafer Stacked Wide I/O DRAM with One-step TSV Technology;2022 IEEE 72nd Electronic Components and Technology Conference (ECTC);2022-05

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