Design of Dynamic comparator using CMOS and FINFET technologies
Author:
Affiliation:
1. VNR Vignana Jyothi Institute of Engineering and Technology,E.C.E Department,Hyderabad,India
2. VNR Vignana Jyothi Institute of Engineering and Technology,VLSI,Hyderabad,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10306338/10306339/10307360.pdf?arnumber=10307360
Reference18 articles.
1. Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator;babayan-mashhadi;EEE Transactions on Very Large Scale Integration (VLSI) Systems,2013
2. SAR ADC Using Low Power High Speed Comparator for Precise Applications;prakash;Jeti,2019
3. A current-mode latch sense amplifier and a static power saving input buffer for low-power architecture
4. A 10 bit SAR ADC With Data-Dependent Energy Reduction Using LSB-First Successive Approximation
5. Finfet Based Two Stage Dynamic Comparators for Low Power High Speed Adcs;musala;Journal International Journal of Recent Technology and Engineering (IJRTE),2019
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