Author:
Abdel-Hafeez Saleh,Harb Shadi M.,Eisenstadt William R.
Cited by
7 articles.
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1. Optimized Parallel Architecture for a Constant-Time Synchronous Binary Counter with Minimal Clock Period;2024 IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS);2024-06-28
2. 64-Bit High Speed Counter with Galois LFSR;2024 International Conference on Circuit, Systems and Communication (ICCSC);2024-06-28
3. Constant-Time Synchronous Binary Counter with Minimal Clock Period;2024 5th International Conference on Recent Trends in Computer Science and Technology (ICRTCST);2024-04-09
4. Power, Performance and Area Optimization of Parallel Load Counters through Logic Minimization and TSPC-FF Utilization;2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS);2023-12-04
5. Performance Enhancement Counter with Minimal Clock Period;E3S Web of Conferences;2023