Author:
Su Tiankai,Yasin Atif,Yu Cunxi,Ciesielski Maciej
Cited by
3 articles.
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1. Aries: A Semiformal Technique for Fine-Grained Bug Localization in Hardware Designs;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2022-12
2. Functional Verification of Arithmetic Circuits: Survey of Formal Methods;2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS);2022-04-06
3. Spectral approach to verifying non-linear arithmetic circuits;Proceedings of the 24th Asia and South Pacific Design Automation Conference;2019-01-21