A Parallel Circuit Design of Chien Search and Forney Algorithm

Author:

Tan Jingxuan1,Zhang Liguo1,Li Xingjin1,Hui Yingzhao1,Ma Jiahui1,Bai Shengfei1

Affiliation:

1. Xi’an University of Posts & Telecommunications,school of electronic engineering,Xi’an,Shaanxi

Publisher

IEEE

Reference16 articles.

1. Erasure-correction-enhanced iterative decoding for LDPC-RS product codes

2. Hardware implementation of Reed-Solomon error correction technique for wireless sensor network based on error pattern analysis

3. Strength-Reduced Parallel Chien Search Architecture for Strong BCH Codes;cho;IEEE Transactions on Circuits and Systems II Express Briefs,2008

4. Research and Improvement of Parallel Money Search in Flash BCH Decoder;ren;Journal of Optoelectronics·Laser,2016

5. Design and Implementation of a 100G EPON System RS Encoder;du;Journal of University of Posts and Telecommunications,2021

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