Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs-Reference-Cited by-同舟云学术

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Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs

Published:2020 Issue: Volume:1 Page:34-47
ISSN:2644-1225
Container-title:IEEE Open Journal of Circuits and Systems
language:
Short-container-title:IEEE Open J. Circuits Syst.

Author:

Mehta Shantanu,O'Hare Daniel,O'Brien Vincent,Thompson Eric,Mullane Brendan

Funder

Enterprise Ireland, Innovation Partnership Project

SFI-CONNECT Science Foundation Ireland

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Medicine

Link

http://xplorestaging.ieee.org/ielx7/8784029/8816702/09094170.pdf?arnumber=9094170

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of Low Power Current Steering DAC Using 45nm CMOS Technology;2024 Third International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE);2024-04-26

2. Design of an Automatic Resonance Frequency Tracking Chip for Power Ultrasonic Transducer With a Center Frequency Below 100 kHz;IEEE Sensors Journal;2023-05-01

3. A 10‐bit 1GSample/s hybrid digital‐to‐analog converter with a modified thermometer decoder in 65‐nm CMOS technology;International Journal of Circuit Theory and Applications;2021-10-30

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