VLSI Implementation of Fully Parallel and CSD FIR Filter Architecture-Reference-Cited by-同舟云学术

VLSI Implementation of Fully Parallel and CSD FIR Filter Architecture

Published:2022-10-20 Issue: Volume: Page:
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Container-title:2022 3rd International Conference on Smart Electronics and Communication (ICOSEC)
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Author:

Prabhavathy M¹,Sakthivel Sm¹

Affiliation:

1. VIT,SENSE,Chennai,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9951706/9951861/09952097.pdf?arnumber=9952097

Reference27 articles.

1. Implementation of a Parallel Prefix Adder Based on Kogge-Stone Tree International Conference on Communications;chen;Information Management and Network Security,0

2. 32-Bit RISC Processor Using Vedic Multiplier;vishnu;2022 3rd International Conference for Emerging Technology (INCET),2022

3. Fully parallel and fully serial architecture for realization of high speed FIR filters with FPGA's

4. VLSI design of efficient FIR filters using Vedic Mathematics and Ripple Carry Adder

5. Implementation of optimized FIR filter using reversible logic gates;janaki ram;CVR Journal of Science and Technology,2020

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