A highly scalable 8-layer Vertical Gate 3D NAND with split-page bit line layout and efficient binary-sum MiLC (Minimal Incremental Layer Cost) staircase contacts-Reference-Cited by-同舟云学术

A highly scalable 8-layer Vertical Gate 3D NAND with split-page bit line layout and efficient binary-sum MiLC (Minimal Incremental Layer Cost) staircase contacts

Published:2012-12 Issue: Volume: Page:
ISSN:
Container-title:2012 International Electron Devices Meeting
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Author:

Chen Shih-Hung,Lue Hang-Ting,Shih Yen-Hao,Chen Chieh-Fang,Hsu Tzu-Hsuan,Chen Yan-Ru,Hsiao Yi-Hsuan,Huang Shih-Cheng,Chang Kuo-Pin,Hsieh Chih-Chang,Lee Guan-Ru,Chuang Alfred-Tung-Hua,Hu Chih-Wei,Chiu Chia-Jung,Lin Lo Yueh,Lee Hong-Ji,Tsai Feng-Nien,Yang Chin-Cheng,Yang Tahone,Lu Chih-Yuan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6471855/6478950/06478963.pdf?arnumber=6478963

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