Dual-channel CMOS co-integration with Si NFET and strained-SiGe PFET in nanowire device architecture featuring sub-15nm gate length-Reference-Cited by-同舟云学术

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Dual-channel CMOS co-integration with Si NFET and strained-SiGe PFET in nanowire device architecture featuring sub-15nm gate length

Published:2014-12 Issue: Volume: Page:
ISSN:
Container-title:2014 IEEE International Electron Devices Meeting
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Author:

Nguyen P.,Barraud S.,Tabone C.,Gaben L.,Casse M.,Glowacki F.,Hartmann J.-M.,Samson M.-P.,Maffini-Alvaro V.,Vizioz C.,Bernier N.,Guedj C.,Mounet C.,Rozeau O.,Toffoli A.,Alain F.,Delprat D.,Nguyen B.-Y.,Mazure C.,Faynot O.,Vinet M.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7038718/7046955/07047062.pdf?arnumber=7047062

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A novel approach to Si0.5Ge0.5 channel FinFET fabrication: utilizing a three-layer SiGe strain relaxation buffer and In-Situ phosphorus doping;Journal of Materials Science: Materials in Electronics;2024-02

2. Si_0.5Ge_0.5 Channel FinFET Preparation on an In Situ Doped SiGe SRB and Its Electrical Characteristics Optimization;ECS Journal of Solid State Science and Technology;2023-03-01

3. Optimization of SiGe interface properties with ozone oxidation and a stacked HfO₂/Al₂O₃ dielectric for a SiGe channel FinFET transistor;Semiconductor Science and Technology;2022-11-04

4. Bias dependent physics-based model of low-frequency noise for nanowire type gate-all-around MOSFETs;Solid-State Electronics;2022-03

5. SiN-based platform toward monolithic integration in photonics and electronics;Journal of Materials Science: Materials in Electronics;2021-01

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