Charge storage efficiency (CSE) effect in modeling the incremental step pulse programming (ISPP) in charge-trapping 3D NAND flash devices
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/7402013/7409598/07409635.pdf?arnumber=7409635
Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Satisfiability Attack-Resilient Camouflaged Multiple Multivariable Logic-in-Memory Exploiting 3D NAND Flash Array;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-02
2. Modeling the Operation of Charge Trap Flash Memory—Part II: Understanding the ISPP Curve With a Semianalytical Model;IEEE Transactions on Electron Devices;2024-01
3. Accurate SPICE Model for Cells With Tube-Type Poly-Si Channel in Cell Strings of Vertical NAND Flash Memory;IEEE Transactions on Electron Devices;2023-10
4. Investigation of the Connection Schemes between Decks in 3D NAND Flash;Micromachines;2023-09-17
5. Investigation of Program Efficiency Overshoot in 3D Vertical Channel NAND Flash with Randomly Distributed Traps;Nanomaterials;2023-04-24
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