Low-Power 8x8 S-RAM Memory Design: CADENCE-Based Simulation and Analysis
Author:
Affiliation:
1. Siddaganga Institute of Technology,Department of ECE,Tumakuru,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10511271/10511093/10512325.pdf?arnumber=10512325
Reference16 articles.
1. VLSI design and analysis of low power 6T SRAM cell using cadence tool
2. Design and Analysis of Two Low-Power SRAM Cell Structures
3. Read stability and Write ability analysis of different SRAM cell structures;Gadhe;International Journal of Engineering Research and Applications (IJERA),2013
4. Low Power SRAM Design with Reduced Read/Write Time;Yadav;International Journal of Information and Computation Technology,2013
5. Design and Analysis of Low Power Static RAM Using Cadence Tool in 180nm Technology;Kumar
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