An Efficient Vectorization Scheme for Stencil Computation
Author:
Affiliation:
1. Chinese Academy of Sciences, Institute of Computing Technology,State Key Laboratory of Computer Architecture,Beijing
Funder
National Natural Science Foundation of China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9820609/9820610/09820707.pdf?arnumber=9820707
Reference39 articles.
1. Exploiting reuse and vectorization in blocked stencil compu-tations on cpus and gpus;zhao;SC'19,2019
2. Vector Folding: Improving Stencil Performance via Multi-dimensional SIMD-vector Representation
3. On the scalability of loop tiling techniques;wonnacott;IMPACT-2013,2013
4. Intel® openmp c++/fortran compiler for hyper-threading technology: Implementation and performance;tian;Intel Technology Journal,2002
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