Securing Hardware Accelerators: A New Challenge for High-Level Synthesis-Reference-Cited by-同舟云学术

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Securing Hardware Accelerators: A New Challenge for High-Level Synthesis

Published:2018-09 Issue:3 Volume:10 Page:77-80
ISSN:1943-0663
Container-title:IEEE Embedded Systems Letters
language:
Short-container-title:IEEE Embedded Syst. Lett.

Author:

Pilato Christian^ORCID,Garg Siddharth,Wu Kaijie,Karri Ramesh^ORCID,Regazzoni Francesco^ORCID

Funder

H2020 European Institute of Innovation and Technology

National Science Foundation

CCS-AD

NYU-AD

Boeing

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Computer Science,Control and Systems Engineering

Link

https://ieeexplore.ieee.org/ielaam/4563995/8449127/8114281-aam.pdf

Cited by 69 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Secure hardware IP of GLRT cascade using color interval graph based embedded fingerprint for ECG detector;Scientific Reports;2024-06-10

2. Guidelines for the Design of Random Telegraph Noise-Based True Random Number Generators;IEEE Transactions on Device and Materials Reliability;2024-06

3. Multi-cut based architectural obfuscation and handprint biometric signature for securing transient fault detectable IP cores during HLS;Integration;2024-03

4. Watermarking Hardware IPs Using Design Parameter Driven Encrypted Dispersion Matrix With Eigen Decomposition Based Security Framework;IEEE Access;2024

5. Designing Optimized and Secured Reusable Convolutional Hardware Accelerator Against IP Piracy Using Retina Biometrics;2023 IEEE International Symposium on Smart Electronic Systems (iSES);2023-12-18

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