A parity bit signature for exhaustive testing-Reference-Cited by-同舟云学术

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A parity bit signature for exhaustive testing

Published:1988-03 Issue:3 Volume:7 Page:333-338
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Akers S.B.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx1/43/179/00003166.pdf?arnumber=3166

Cited by 22 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design a Low Power and High Speed Parity Checker using Exclusive–or Gates;International Journal of Innovative Technology and Exploring Engineering;2021-02-28

2. ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2020-04

3. An ALU Protection Methodology for Soft Processors on SRAM-Based FPGAs;IEEE Transactions on Computers;2019-09-01

4. On a New Graph Theory Approach to Designing Zero-Aliasing Space Compressors for Built-In Self-Testing;IEEE Transactions on Instrumentation and Measurement;2008-10

5. Aliasing-free compaction revisited;IET Circuits, Devices & Systems;2008

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