Design and Investigation of Stacked Nanosheet Transistor Parameters for Analog Performance
Author:
Affiliation:
1. National Institute of Technology,Srinagar Garhwal,Electronics Engineering Department,Uttarakhand,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10110034/10110036/10110055.pdf?arnumber=10110055
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1. Impact of additional factors in threshold voltage variability of metal/high-k gate stacks and its reduction by controlling crystalline structure and grain size in the metal gates
2. Design Insights of Nanosheet FET and CMOS Circuit Applications at 5-nm Technology Node
3. Investigation of Electrical Characteristic Behavior Induced by Channel-Release Process in Stacked Nanosheet Gate-All-Around MOSFETs
4. On the impact of TiN film thickness variations on the effective work function of poly-Si/TiN/SiO/sub 2/ and poly-Si/TiN/HfSiON gate stacks
5. ATLAS User’s Manual Device Simulation Software,2004
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