A fractional-N DPLL with adaptive spur cancellation and calibration-free injection-locked TDC in 65nm CMOS
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/6844558/6851613/06851668.pdf?arnumber=6851668
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Canceling Fundamental Fractional Spurs Due to Self-Interference in a Digital Phase-Locked Loop;IEEE Journal of Solid-State Circuits;2024
2. A 1.9-ps 8× phase interpolation TDC for time-based analog-to-digital converter with capacitance compensation self-calibration;IEICE Electronics Express;2023-02-10
3. A 1.9-ps 8x Phase Interpolation TDC for Time-based Analog-to- Digital Converter with Capacitance Compensation Self-Calibration;IEICE ELECTRON EXPR;2023
4. A Flash-Based Non-Uniform Sampling ADC With Hybrid Quantization Enabling Digital Anti-Aliasing Filter;IEEE Journal of Solid-State Circuits;2017-09
5. DPLL for Phase Noise Cancellation in Ring Oscillator-Based Quadrature Receivers;IEEE Journal of Solid-State Circuits;2017-04
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