A fully synthesizable single-precision, floating-point adder/substractor and multiplier in VHDL for general and educational use

Author:

Marcus G.,Hinojosa P.,Avila A.,Nolazco-Flores J.

Publisher

IEEE

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. FPGA Implementation of IIR Notch and Anti-Notch Filters With an Application to Localization of Protein Hot-Spots;IEEE Transactions on NanoBioscience;2023-10

2. SwiftTron: An Efficient Hardware Accelerator for Quantized Transformers;2023 International Joint Conference on Neural Networks (IJCNN);2023-06-18

3. Logic Design and Power Optimization of Floating-Point Multipliers;Computational Intelligence and Neuroscience;2022-01-07

4. Low-Power and Area-Efficient Design of Higher-Order Floating-Point Multipliers Using Vedic Mathematics;Lecture Notes in Electrical Engineering;2019-09-25

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