Defensive loop tiling for shared cache-Reference-Cited by-同舟云学术

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Defensive loop tiling for shared cache

Published:2013-02 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)
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Author:

Bin Bao ,Chen Ding

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6489844/6494968/06495008.pdf?arnumber=6495008

Cited by 21 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Characterizing the Performance of Emerging Deep Learning, Graph, and High Performance Computing Workloads Under Interference;2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW);2024-05-27

2. PinIt: Influencing OS Scheduling via Compiler-Induced Affinities;Proceedings of the 24th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems;2023-06-13

3. Designing Secure Performance Metrics for Last Level Cache;2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW);2023-05

4. Data Locality in High Performance Computing, Big Data, and Converged Systems: An Analysis of the Cutting Edge and a Future System Architecture;Electronics;2022-12-23

5. A Methodology for Efficient Tile Size Selection for Affine Loop Kernels;International Journal of Parallel Programming;2022-05-23

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