Design and Performance Analysis of 10T SRAM Cell Using Dopingless Vertical Nanowire Tunnel FET with NC Effect
Author:
Affiliation:
1. ASET Amity University,Dept. of ECE,Uttar Pradesh,India
2. NIT,Dept. of ECE,Jalandhar,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10560064/10560065/10560137.pdf?arnumber=10560137
Reference13 articles.
1. Design and Performance Analysis of a GAA Electrostatic Doped Negative Capacitance Vertical Nanowire Tunnel FET
2. Random Dopant Fluctuation in Limited-Width FinFET Technologies
3. Design and optimization of vertical nanowire tunnel FET with electrostatic doping
4. Comparison of Performance Analysis of 6T, 7T, 8T, 9T and 10T-SRAM Cells;Satheesh;Terms Of Low Power Dissipation and Delay. Think India Journal,2019
5. Implementation of CMOS SRAM Cells in 7 8 10and 12- Transistor Topologies and their performance Comparison;Kumar;International J oumal of Engineering and Advanced Technology,2019
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