Evaluation of Soft Error Tolerance on Flip-Flops Restoring from a Single Node Upset by C-elements
Author:
Affiliation:
1. Kyoto Institute of Technology,Department of Electronics,Kyoto,Japan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9975349/9975304/09975373.pdf?arnumber=9975373
Reference6 articles.
1. Soft-Error Tolerance Depending on Supply Voltage by Heavy Ions on Radiation-Hardened Flip Flops in a 65 nm Bulk Process
2. An Area-Efficient 65 nm Radiation-Hard Dual-Modular Flip-Flop to Avoid Multiple Cell Upsets
3. Impact of CMOS technology scaling on the atmospheric neutron soft error rate
4. Radiation hardened flip-flops minimizing area, power, and delay overheads with 1/100 lower alphaser in a 130 nm bulk process;nakajima;IEEE International Symposium on On-Line Testing and Robust System Design,2022
5. Combinational Logic Soft Error Correction
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