Study of ESD Reliability on Gate and Drain to Source and substrate Stress by Structure Modulation in 0.18 μm 6 V nLDMOS Devices-Reference-Cited by-同舟云学术

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Study of ESD Reliability on Gate and Drain to Source and substrate Stress by Structure Modulation in 0.18 μm 6 V nLDMOS Devices

Published:2022-10-14 Issue: Volume: Page:
ISSN:
Container-title:2022 IET International Conference on Engineering Technologies and Applications (IET-ICETA)
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Author:

Chen Hsun-Hsiang¹,Zhang You¹,Chen Shen-Li²

Affiliation:

1. National Changmhua University of Education,Department of Electronic Engineering,Changhua,Taiwan

2. National United University,Department of Electronic Engineering,Miaoli,Taiwan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9971143/9971472/09971637.pdf?arnumber=9971637

Reference6 articles.

1. Evaluating the Drift-Region Length Effect of nLDMOS on ESD Ability with a TLP Testing System

2. A novel SCR-LDMOS for high voltage ESD protection;jing;Proceedings - 2015 IEEE 11th International Conference on ASIC ASICON 2015,2016

3. ESD Improvements on Power N-Channel LDMOS Devices by the Composite Structure of Super Junctions Integrated With SCRs in the Drain Side

4. ESD Immunity Impacts of the Drain-Side Heterojunction Device Addition in HV 60 V n/pLDMOS Devices

5. High-Voltage LDMOS With Charge-Balanced Surface Low On-Resistance Path Layer

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