ESD-immunity Study of High-voltage nLDMOS with Vertical Parasitic Schottky Structures in the Source End
Author:
Affiliation:
1. National United University,Department of Electronic Engineering,Taiwan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9971143/9971472/09971482.pdf?arnumber=9971482
Reference4 articles.
1. Low-trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering
2. ESD Protection Design for Touch Panel Control IC Against Latchup-Like Failure Induced by System-Level ESD Test
3. Investigation of Unexpected Latchup Path Between HV-LDMOS and LV-CMOS in a 0.25- $\mu \text{m}$ 60-V/5-V BCD Technology
4. A Novel Drain Design for ESD Improvement of UHV-LDMOS
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