Author:
Fezzardi Pietro,Castellana Michele,Ferrandi Fabrizio
Cited by
16 articles.
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1. A High Level Synthesis Methodology for Dynamic Monitoring of FPGA ML Accelerators;2024 IEEE 42nd VLSI Test Symposium (VTS);2024-04-22
2. DiffLo: A Graph-based Method for Functional Discrepancy Localization in High-level Synthesis;2023 International Conference on Field Programmable Technology (ICFPT);2023-12-12
3. mu-grind;Proceedings of the International Conference on Parallel Architectures and Compilation Techniques;2022-10-08
4. Accelerator Design with High-Level Synthesis;Handbook of Computer Architecture;2022
5. FastSim: A Fast Simulation Framework for High-Level Synthesis;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2021