Bandwidth-Efficient Sparse Matrix Multiplier Architecture for Deep Neural Networks on FPGA
Author:
Affiliation:
1. Indian Institute of Information Technology Kottayam,Kerala,India
2. Cochin University of Science And Technology,Kerala,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9739206/9739211/09739346.pdf?arnumber=9739346
Reference21 articles.
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