Performance Enhancement of SoC with Five Port Router by Replacing APB Protocol
Author:
Affiliation:
1. Bannari Amman Institute of Technology,Tamilnadu,India
2. Bannari Amman Institute of Technology,Department of ECE,Tamilnadu,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10009016/10009051/10009627.pdf?arnumber=10009627
Reference9 articles.
1. Performance evalulation of different routing algorithms in Network on Chip
2. Examining the Performance Impact of NoC Parameters for Scalable and Adaptive FPGA-Based Network-on-Chips
3. Design and implementation of a dynamic weight arbiter for networks-on-chip
4. Design and analysis of a mesh-based Adaptive Wireless Network-on Chips Architecture with Irregular Network Routing
5. Performance enhancement and area optimization of 3×3 NoC using random arbiter
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