Accelerators in Embedded Systems for Machine Learning: A RISCV View

Author:

Sanchez-Flores Alejandra1,Alvarez Lluc2,Alorda-Ladaria Bartomeu3

Affiliation:

1. Universitat de les Illes Balears,Industrial and Construction Eng. Dept.,Palma,Spain

2. Universitat Politècnica de Catalunya,Barcelona Supercomputing Center,Barcelona,Spain

3. Universitat de les Illes Balears,Inst. de Inv. Sanitaria IB - IdisBa. Inst. Agro. y Eco. Agua – INAGEA,Industrial and Construction Eng. Dept.,Palma,Spain

Funder

Instituto de Salud Carlos III

Generalitat de Catalunya

Publisher

IEEE

Reference37 articles.

1. RVCoreP-32IM: An effective architecture to implement mul/div instructions for five stage RISC-V soft processors;Islam,2020

2. Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications

3. Z-scale: Tiny 32-bit RISC-V Systems;Yunsup Lee

4. Optimizing RISC-V ISA Usage by Sharing Coprocessors on MPSoC

5. Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices

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