A High Throughput Hardware Architecture Targeting the AV1 Paeth Intra Predictor-Reference-Cited by-同舟云学术

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A High Throughput Hardware Architecture Targeting the AV1 Paeth Intra Predictor

Published:2019-02 Issue: Volume: Page:
ISSN:
Container-title:2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)
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Author:

Correa Marcel,Waskow Bianca,Goebel Jones,Palomino Daniel,Correa Guilherme,Agostini Luciano

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8666669/8667535/08667544.pdf?arnumber=8667544

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Exploring AV1 Encoder Potentials for Priority-Driven Wireless Multimedia Services;2022 Intermountain Engineering, Technology and Computing (IETC);2022-05

2. Power-Quality Configurable Hardware Design for AV1 Directional Intraframe Prediction;IEEE Design & Test;2022-04

3. Configurable Power/Quality-Aware Hardware Design for the AV1 Directional Intra Frame Prediction;2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI);2021-08-23

4. Exploring Operation Sharing in Directional Intra Frame Prediction of AV1 Video Coding;2021 IEEE 12th Latin America Symposium on Circuits and System (LASCAS);2021-02-21

5. AV1 and VVC Video Codecs: Overview on Complexity Reduction and Hardware Design;IEEE Open Journal of Circuits and Systems;2021

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