High Audio Band PSR and Fast Settling-Time Dual-Loop LDO Regulator Architecture for Low-Power Application-Reference-Cited by-同舟云学术

High Audio Band PSR and Fast Settling-Time Dual-Loop LDO Regulator Architecture for Low-Power Application

Published:2021-12-09 Issue: Volume: Page:
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Container-title:2021 International Conference on Electrical, Computer and Energy Technologies (ICECET)
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Author:

Barteselli Edoardo¹,Sant Luca²,Gaggl Richard²,Baschirotto Andrea¹

Affiliation:

1. University of Milano - Bicocca,Physics Dept. “G. Occhialini”,Milan,Italy

2. Infineon Technologies,Villach,Austria

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9698246/9698247/09698752.pdf?arnumber=9698752

Reference10 articles.

1. A fast transient LDO based on dual loop FVF with high PSRR

2. A 22dB PSRR enhancement in a two-stage CMOS opamp using tail compensation

3. A High Power Low Dropout Voltage Regulator Design with an Enhanced Resistive Bank Circuit for Powering an RF IC for DSRC Applications;ul ain;2020 35th International Technical Conference on Circuits/Systems Computers and Communications (ITC-CSCC),2020

4. A Fast Transient Response LDO without on-chip Compensated Capacitor

5. High-Voltage Double-Domain Low-Dropout regulator for rapidly changing output loads

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1. A 55nm, Multiple-Loop, Fast-Transient, −76.2 dB Worst-Case PSRR LDO for High-End Audio Circuits;2024 19th Conference on Ph.D Research in Microelectronics and Electronics (PRIME);2024-06-09

2. A low power LDO with high PSR over a wide frequency range based on an impedance attenuation buffer;IEICE Electronics Express;2024-03-25

3. Voltage Reference Generator for Audio Interface in 55nm CMOS Technology Node;2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS);2023-12-04

4. An Ultra-Fast Transient Digital-LDO with Adaptive Rising-Edge Logic Control;2023 8th International Conference on Integrated Circuits and Microsystems (ICICM);2023-10-20