Cryogenic Hysteresis in 110 nm Bulk Silicon MOSFETs for Capacitorless Memory Applications-Reference-Cited by-同舟云学术

Cryogenic Hysteresis in 110 nm Bulk Silicon MOSFETs for Capacitorless Memory Applications

Published:2023-09 Issue:9 Volume:44 Page:1543-1546
ISSN:0741-3106
Container-title:IEEE Electron Device Letters
language:
Short-container-title:IEEE Electron Device Lett.

Author:

Zhang Yuanke¹^ORCID,Chen Yuefeng¹,Huang Jixiang¹,Sun Shuyang¹^ORCID,Xu Jun¹,Luo Chao¹^ORCID,Guo Guoping²^ORCID

Affiliation:

1. Department of Physics, CAS Key Laboratory of Quantum Information, University of Science and Technology of China, Hefei, China

2. Department of Physics, Hefei National Laboratory and the CAS Key Laboratory of Quantum Information, University of Science and Technology of China, Hefei, China

Funder

National Natural Science Foundation of China

Innovation Program for Quantum Science and Technology

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/55/10230308/10179943.pdf?arnumber=10179943

Reference35 articles.

1. A cryo-CMOS chip that integrates silicon quantum dots and multiplexed dispersive readout electronics

2. Cryo-CMOS for quantum computing

3. Cryo-CMOS Circuits and Systems for Quantum Computing Applications

4. Evidence of Tunneling Driven Random Telegraph Noise in Cryo-CMOS

5. Cryogenic characterization of 28 nm bulk CMOS technology for quantum computing

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