Impact of Trapped-Charge Variations on Scaled Ferroelectric FET Nonvolatile Memories

Author:

Liu You-Sheng,Su Pin

Funder

Ministry of Science and Technology, Taiwan

“Center for Semiconductor Technology Research” from the Featured Areas Research Center Program within the framework of the Higher Education Sprout Project by the Ministry of Education, Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Cited by 15 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Hybrid-Precision Synapse Based-on FDSOI FeFETs With Back-Gate Bias Modulation;IEEE Transactions on Electron Devices;2024-06

2. Design Guidelines of Hafnia Ferroelectrics and Gate-Stack for Multilevel-Cell FeFET;IEEE Transactions on Electron Devices;2024-03

3. Impact of Random Interface Traps Fluctuation on Device Variation of Oxide-Semiconductor Ferroelectric Field-Effect Transistor Memories;IEEE Electron Device Letters;2023-12

4. Monte-Carlo Based Simulation Method for Ferroelectric Memory Devices Including Polarization Switching and Trap Behaviors;2023 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD);2023-09-27

5. Impact of Interface Trap Density on the Endurance of HFO2/SI FEFETS;2023 China Semiconductor Technology International Conference (CSTIC);2023-06-26

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