Tempo-CIM: A RRAM Compute-in-Memory Neuromorphic Accelerator With Area-Efficient LIF Neuron and Split-Train-Merged-Inference Algorithm for Edge AI Applications-Reference-Cited by-同舟云学术

Tempo-CIM: A RRAM Compute-in-Memory Neuromorphic Accelerator With Area-Efficient LIF Neuron and Split-Train-Merged-Inference Algorithm for Edge AI Applications

Published:2023-12 Issue:4 Volume:13 Page:986-999
ISSN:2156-3357
Container-title:IEEE Journal on Emerging and Selected Topics in Circuits and Systems
language:
Short-container-title:IEEE J. Emerg. Sel. Topics Circuits Syst.

Author:

Jiang Jingwen¹^ORCID,Zhou Keji¹^ORCID,Liang Jinhao¹,Tian Fengshi²,Zhao Chenyang¹^ORCID,Yang Jianguo³^ORCID,Xue Xiaoyong¹^ORCID,Zeng Xiaoyang¹

Affiliation:

1. State Key Laboratory of Integrated Chips and Systems, School of Microelectronics, Fudan University, Shanghai, China

2. ECE Department, The Hong Kong University of Science and Technology (HKUST), Hong Kong, China

3. Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, China

Funder

STI 2030—Major Projects

National Natural Science Foundation of China

Science and Technology Commission of Shanghai Municipality

Opening Project of Zhejiang Laboratory

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/5503868/10375869/10268434.pdf?arnumber=10268434

Reference54 articles.

1. Model Compression and Acceleration for Deep Neural Networks: The Principles, Progress, and Challenges

2. Towards spike-based machine intelligence with neuromorphic computing

3. 7.6 A 65nm 236.5nJ/Classification Neuromorphic Processor with 7.5% Energy Overhead On-Chip Learning Using Direct Spike-Only Feedback

4. C-DNN: A 24.5-85.8TOPS/W Complementary-Deep-Neural-Network Processor with Heterogeneous CNN/SNN Core Architecture and Forward-Gradient-Based Sparsity Generation

5. In-memory computing with resistive switching devices

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An 11T1C Bit-Level-Sparsity-Aware Computing-in-Memory Macro With Adaptive Conversion Time and Computation Voltage;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

2. Guest Editorial Dynamical Neuro-AI Learning Systems: Devices, Circuits, Architecture and Algorithms;IEEE Journal on Emerging and Selected Topics in Circuits and Systems;2023-12