A CMOL-Like Memristor-CMOS Neuromorphic Chip-Core Demonstrating Stochastic Binary STDP
Author:
Affiliation:
1. Instituto de Microelectrónica de Sevilla (IMSE-CNM), Spanish Research Council (CSIC), Universidad de Sevilla, Seville, Spain
2. CEA-LETI, Grenoble, France
Funder
EU H2020
“MeM-Scales;”
Spain’s Ministry of Science and Innovation
European Regional Development Fund
VI PPIT through the Universidad de Sevilla
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/5503868/9991262/09894418.pdf?arnumber=9894418
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1. A compute-in-memory chip based on resistive random-access memory
2. 33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models
3. Immunity to Device Variations in a Spiking Neural Network With Memristive Nanodevices
4. Bio-Inspired Stochastic Computing Using Binary CBRAM Synapses
5. Extraction of temporally correlated features from dynamic vision sensors with spike-timing-dependent plasticity
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