LUT Cascades Based on Edge-Valued Multi-Valued Decision Diagrams: Application to Packet Classification
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/5503868/7429966/7415981.pdf?arnumber=7415981
Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Fast Update Algorithm With Reorder Mechanism for SRAM-Based Longest Prefix Matching on FPGA;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-01
2. PackeX: Low-Power High-Performance Packet Classifier Using Memory on FPGAs;Wireless Communications and Mobile Computing;2021-06-07
3. Comp-TCAM: An adaptable composite Ternary content-addressable Memory on FPGAs;IEEE Embedded Systems Letters;2021
4. Common non-wildcard portion-based partitioning approach to SDN many-field packet classification;Computer Networks;2020-11
5. DURE: An Energy- and Resource-Efficient TCAM Architecture for FPGAs With Dynamic Updates;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2019-06
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