A Low Jitter Digital Loop CDR Based 8–16 Gbps SerDes in 65 nm CMOS Technology-Reference-Cited by-同舟云学术

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A Low Jitter Digital Loop CDR Based 8–16 Gbps SerDes in 65 nm CMOS Technology

Published:2021-02 Issue: Volume: Page:
ISSN:
Container-title:2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID)
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Author:

Sen Souradip,Upadhyaya Utkarsh,Kondreddy Krishna Reddy,Goyal Arun,Goyal Sandeep,Gupta Shalabh

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9407329/9407276/09407485.pdf?arnumber=9407485

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design High Frequency Phase Locked Loop Using Single Ended VCO for High Speed Applications;2022 IEEE Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI);2022-12-21

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