Design of High-Speed Adder with three operands for Image Blending Applications-Reference-Cited by-同舟云学术

Design of High-Speed Adder with three operands for Image Blending Applications

Published:2023-06-16 Issue: Volume: Page:
ISSN:
Container-title:2023 2nd International Conference on Advancements in Electrical, Electronics, Communication, Computing and Automation (ICAECA)
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Author:

Gayathree K.¹,Niranjana M. Ishwarya²,D Ram Nivas.³,Umamaheswari K.¹,Dhanasekar J.²,Shankar J. Vishnu¹

Affiliation:

1. Dr. Mahalingam College of Engineering and Technology,Department of Electronics and Communication Engineering,Pollachi,India

2. Sri Eshwar College of Engineering and Technology,Department of Electronics and Communication Engineering,Coimbatore,India

3. KPR Institute of Engineering and Technology,Electronics and Communication Engineering,Coimbatore,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10199105/10199188/10200988.pdf?arnumber=10200988

Reference14 articles.

1. A robust single ended 10 T Schmitt Trigger based SRAM cell with enhanced read/write assist techniques;gayathree;Int J Pure Appl Math,2018

2. Improved modified area efficient carry select adder (MAE- CSLA) without multiplexer;teresa;Journal of Computational and Theoretical Nano science,2017

3. A Novel Design Of Current Mode Multiplier/Divider Circuits For Analog Signal Processing;mohankumar;International Journal of Computer Science and Mobile Computing,2014

4. Design of low power 4-bit Carry Look Ahead adder using self resetting and gate diffusion input logics;dhanasekar;Solid State Technology,0

5. Energy-efficient high-throughput Montgomery modular multipliers for RSA cryptosystems;chang;IEEE Trans Very Large-Scale Integration,2013

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