Design of Various Modulation Schemes using DDS-Reference-Cited by-同舟云学术

Design of Various Modulation Schemes using DDS

Published:2023-02-23 Issue: Volume: Page:
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Container-title:2023 7th International Conference on Computing Methodologies and Communication (ICCMC)
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Author:

Jothimani S.¹,Narmadha A.¹,Santhiya C.¹,Priya S.SHANMUGA¹

Affiliation:

1. Electronics and Communication Engineering M.Kumarasamy College of Engineering,Karur,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10083318/10083503/10083652.pdf?arnumber=10083652

Reference17 articles.

1. Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector

2. A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by $N ^{2}$

3. A2.2 GHz sub-samplingPLLwith 0.16psrms jitter and -125dBc/Hz in-band phase noise at 700µW loop-components power;gao;Proc IEEE VLSI Circuits Symp,2010

4. A Type-I Sub-Sampling PLL With a $100\times100\,\,\mu\text{m}^{2}$ Footprint and −255-dB FOM

5. Estimating SecuritiesExchange Utilizing Profound Neural Networks;jothimani;International Journal of Grid and Distributed Computing,2019

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