FPGA Implementation Of a High Throughput Low Power Advanced Encryption Standard (AES-128) Cipher
Author:
Affiliation:
1. Delhi Technological University,Department of Electronics and Communication,New Delhi,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10115458/10115464/10116674.pdf?arnumber=10116674
Reference20 articles.
1. Integrated design of AES (Advanced Encryption Standard) encrypter and decrypter;lu;Proceedings IEEE International Conference on Application-Specific Systems Architectures and Processors,2002
2. AES-128 Based Secure Low Power Communication for LoRaWAN IoT Environments
3. Low latency VLSI architecture of S-box for AES encryption
4. Image Encryption Based on AES Key Expansion
5. A 66.1 Gbps single-pipeline AES on FPGA
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1. Design of VLSI Architecture Using AES Algorithm;2024 3rd International Conference on Artificial Intelligence For Internet of Things (AIIoT);2024-05-03
2. FPGA-based Low-Power Encryption using the Elliptic Curve Digital Signature Algorithm;2023 2nd International Conference on Automation, Computing and Renewable Systems (ICACRS);2023-12-11
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