Minimizing total area of low-voltage SRAM arrays through joint optimization of cell size, redundancy, and ECC
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx5/5640356/5647518/05647605.pdf?arnumber=5647605
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4. Optimal Selection of SRAM Bit-Cell Size for Power Reduction in Video Compression;IEEE Journal on Emerging and Selected Topics in Circuits and Systems;2018-09
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