A Modified Partial Product Generator for Redundant Binary Multipliers

Author:

Cui Xiaoping,Liu Weiqiang,Chen Xin,Swartzlander Earl E.,Lombardi Fabrizio

Funder

National Natural Science Foundation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Cited by 29 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

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2. Area, Delay, and Energy-Efficient Full Dadda Multiplier;Journal of Circuits, Systems and Computers;2023-05-11

3. Realization of High Performance Approximate Multipliers for FPGA Application;2023 International Conference on Recent Advances in Electrical, Electronics, Ubiquitous Communication, and Computational Intelligence (RAEEUCCI);2023-04-19

4. Low Power Radix-4 Booth Multiplier Design Using Pass Transistor Logic;VLSI, Communication and Signal Processing;2023

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