Implementation of FIFO design using Verilog HDL to avoid data losses in transmission-Reference-Cited by-同舟云学术

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Implementation of FIFO design using Verilog HDL to avoid data losses in transmission

Published:2024-04-02 Issue: Volume:7 Page:1-6
ISSN:
Container-title:2024 2nd International Conference on Networking and Communications (ICNWC)
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Author:

Seetharaman R.¹,Ruban P. S. Harsha²,Shiney S. Arumai³,Subramanian L. Harihara⁴,Ganeshakumar M.¹,Adityaa R.¹,Gayathri S.⁵

Affiliation:

1. CEG Campus, Anna University,Department of ECE,Chennai,India,600025

2. Sri Krishna College of Engineering and Technology,Department of ECE,Coimbatore,India,641008

3. S.A.Engineering College,Department of CSE,Chennai,India,600077

4. CEG Campus, Anna University,Department of Management Studies,Chennai,India,600025

5. CEG Campus, Anna University,Department of EEE,Chennai,India,600025

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10537254/10537235/10537600.pdf?arnumber=10537600

Reference15 articles.

1. Asynchronous FIFO design using Verilog;Lincy;Int. Res. J. Eng. Technol,2020

2. Verilog HDL quick reference Guide, Based on the Verilog 2001 standard;Sutherland;IEEE standard

3. UART Based reliable communication and performance analysis;Hu;Computer Engineering,2006

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