18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface-Reference-Cited by-同舟云学术

18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface

Published:2016-01 Issue: Volume: Page:
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Container-title:2016 IEEE International Solid-State Circuits Conference (ISSCC)
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Author:

Lee Jong Chern,Kim Jihwan,Kim Kyung Whan,Ku Young Jun,Kim Dae Suk,Jeong Chunseok,Yun Tae Sik,Kim Hongjung,Cho Ho Sung,Kim Yeon Ok,Kim Jae Hwan,Kim Jin Ho,Oh Sangmuk,Lee Hyun Sung,Kwon Ki Hun,Lee Dong Beom,Choi Young Jae,Lee Jeajin,Kim Hyeon Gon,Chun Jun Hyun,Oh Jonghoon,Lee Seok Hee

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7405163/7417881/7418035.pdf?arnumber=7418035

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