Orthogonal partitioning and gated clock architecture for low power realization of FSMs-Reference-Cited by-同舟云学术

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Orthogonal partitioning and gated clock architecture for low power realization of FSMs

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Container-title:Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541)
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Author:

Shelar R.S.,Narayanan H.,Desai M.P.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/7065/19050/00880713.pdf?arnumber=880713

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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3. Elastic Management and QoS Provisioning Scheme for Adaptable Multi-core Protocol Processing Architecture;2016 Euromicro Conference on Digital System Design (DSD);2016-08

4. Minimization of power consumption of finite state machines by splitting their internal states;Journal of Computer and Systems Sciences International;2015-05

5. Finite State Machine Decomposition for Low Power;IETE Journal of Research;2006-01

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