Various SRAM Condition to Design the FINFET with Operating of Different Condition in Voltage-Reference-Cited by-同舟云学术

Various SRAM Condition to Design the FINFET with Operating of Different Condition in Voltage

Published:2022-03-29 Issue: Volume: Page:
ISSN:
Container-title:2022 6th International Conference on Computing Methodologies and Communication (ICCMC)
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Author:

P Garry Thomson.¹,Muthumanickam T.²,Sheela T.²,SureshKumar G.²

Affiliation:

1. Vinayaka Mission’s Research Foundation (Deemed to be University),Vinayaka Mission’s Kirupananda Variyar Engineering College,M.E Vlsi Design, Department of Electronics and Communication Engineering,Salem,Tamilnadu,India,636308

2. Vinayaka Mission’s Research Foundation (Deemed to be University),Vinayaka Mission’s Kirupananda Variyar Engineering College,Department of Electronics and Communication Engineering,Salem,Tamilnadu,India,636308

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9752772/9753686/09753807.pdf?arnumber=9753807

Reference17 articles.

1. Single bit-line 8T SRAM cell with asynchronous dual word-line control for bit -interleaved ultra-low voltage operation;huang;IET Circuits Devices Syst,2018

2. Performance Analysis Of Mantissa Multiplier And Dadda Tree Multiplier And Implementing With Dsp Architecture

3. Ultra-Low Standby Power SRAM with Adaptive Data-Retention-Voltage-Regulating Scheme

4. Half-Select Free and Bit-Line Sharing 9T SRAM for Reliable Supply Voltage Scaling

5. Ultra-Low Standby Power SRAM with Adaptive Data-Retention-Voltage-Regulating Scheme

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