Performance Modeling of a Reconfigurable Shared Buffer for High-Speed Switch/Router-Reference-Cited by-同舟云学术

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Performance Modeling of a Reconfigurable Shared Buffer for High-Speed Switch/Router

Published:2008 Issue: Volume: Page:
ISSN:
Container-title:2008 IEEE International Conference on Communications
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Author:

Wu L.,Li C.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4533035/4533036/04534099.pdf?arnumber=4534099

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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3. Techniques Analysis for Implementing Shared Relocatable Buffers Using the TMS320 DSP Algorithm Standard;2009 International Conference on Networking and Digital Society;2009-05

4. Architecture design, performance analysis and VLSI implementation of a reconfigurable shared buffer for high-speed switch/router;International Journal of Communication Systems;2009-02

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