10-bit Area-reduced DAC for EIT Applications Using 180 nm Technology-Reference-Cited by-同舟云学术

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10-bit Area-reduced DAC for EIT Applications Using 180 nm Technology

Published:2023-10-10 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE Seventh Ecuador Technical Chapters Meeting (ECTM)
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Author:

Kuribara Vitor O.¹,Junior Marcus H. V.¹,Moreira Luiz C.²,Oliveira Walter S.¹,Nascimento Felipe F.¹,Sanches Bruno C. de S.³,Ponchet André Da F.¹,Palacio Jose A. A.⁴,Van Noije Wilhelmus A. M.³

Affiliation:

1. Aeronautics Institute of Technology São José dos Campo,Department of Applied Electronics,Brazil

2. Catholic University of Santos,Center for Exact Sciences,Santos,Brazil

3. University of São Paulo,Electronic Systems Engineering,São Paulo,Brazil

4. Santander Industrial University,School of Electrical Engineering,Bucaramanga,Colombia

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10308946/10308798/10309058.pdf?arnumber=10309058

Reference12 articles.

1. New single-clock CMOS latches and flipflops with improved speed and power savings

2. Signal Generator for Applying Electrical Bioimpendance Spectroscopy in Cancer Detection;palacio;Ph D thesis,2017

3. A 10-b 70-MS/s CMOS D/A converter

4. ;A CMOS Sub-threshold W-2W Current mode Digitalto-Analog Converter;raby;Master’s thesis,2019

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